As an Advanced Packaging Engineer, you will focus on emerging packaging technologies essential for the scaling of superconducting quantum processors and associated components. You will pioneer innovative packaging methods such as 2.5D/3D integration and novel interconnect technologies. You will collaborate closely with the quantum processor team and RF engineers. Your goal will be to transition research concepts into deployable packaging solutions that enable the scaling roadmap of our quantum processors and quantum computing systems.
The full potential of quantum computing will be unlocked with a large-scale computer capable of complex, error-corrected computations. Google Quantum AI's mission is to build this computer and unlock solutions to classically intractable problems. Our roadmap is focused on advancing the capabilities of quantum computing and enabling meaningful applications.Individual pay is determined by factors including job-related skills, experience, and relevant education or training.US: $159000 - $230000 (USD) + 15% bonus target + equity + benefits
Learn more about benefits at Google.
Responsibilities
- Design, architect, and implement novel packaging platforms.
- Investigate and characterize electrical, thermal, and mechanical properties of packaging materials.
- Develop and document new process flows and Design-For-Integration (DfI) principles for emerging technologies.
- Lead technical engagements with external vendors and partners to evaluate, co-develop, and qualify next-generation packaging processes and components outside of the current standard manufacturing processes.
- Conduct root cause analysis and develop mitigation strategies for performance-limiting factors (e.g., yield, reliability, signal integrity) unique to those new technologies.
Minimum qualifications:
- Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, Physics, or a specialized field (e.g., Optics, Sensors, Audio/DSP, etc.), or equivalent practical experience.
- 5 years of experience in 3 of the following areas of packaging development: simulation, layout and design, process engineering, assembly, test and measurement, failure analysis.
- 5 years of experience with one or more of the following technologies: 2.5D/3D integration, wafer level packaging, panel level packaging, bump bonding.
- 3 years of experience delivering R&D concepts to a released product.
- 3 years of experience developing advanced packaging solutions.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering, Physics, or a related field (e.g., Optics, Sensors, Audio/DSP).
- Experience in a semiconductor packaging environment.
- Experience using simulation tools to evaluate electrical/RF, thermal, or mechanical performance of packaging structures and guide new designs.
- Familiarity with quantum computing hardware architectures and the specific constraints they impose on packaging design.