In this role, you will join an IP and subsystem design team building foundational custom silicon for Google Cloud, rather than focusing solely on standalone block coding or chip-level assembly, blends Register-Transfer Level (RTL) micro-architecture with complex IP and subsystem integration. You will architect and implement custom wrappers, bridges, protocol adapters, and control, interrupt, and debug infrastructure to integrate third-party vendor IPs and internal blocks such as high-speed Peripheral Component Interconnect Express (PCIe) subsystems into cohesive, production-ready designs.
You will help modernize how we build silicon beyond RTL development, create and refine scripting and design automation flows that streamline large-scale IP assembly, configuration, and sign-off, while actively adopting and shaping advanced AI-powered and agentic workflows across hardware design, integration, and debug. You will partner closely with architecture, verification, physical implementation, Design for Test (DFT), software, and external IP vendors, you will drive Power, Performance, and Area (PPA) trade-offs from initial specification through silicon bring-up.Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next-generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Responsibilities
- Define IP and subsystem micro-architecture specifications, including interface protocols, block diagrams, clocking and reset schemes, register maps, and transaction flows.
- Integrate complex third-party vendor IPs and internal blocks (such as PCIe subsystems), developing custom SystemVerilog RTL wrappers, glue logic, and protocol adapters.
- Execute RTL quality sign-off and debug across functional and performance simulation, Lint, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), Formal Verification, and Unified Power Format (UPF) checks.
- Build and enhance design automation, RTL assembly tooling, and AI-assisted hardware engineering workflows to accelerate integration velocity and design quality.
- Collaborate with architecture, verification, physical design, DFT, firmware, and external IP vendors on synthesis, timing and power (PPA) closure, coverage analysis, and ASIC silicon bring-up.
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent practical experience.
- 8 years of experience in digital logic design and RTL development using Verilog or SystemVerilog.
- Experience with IP integration, subsystem design, or System-on-Chip (SoC) architecture.
- Experience with logic synthesis, timing closure, and low-power design techniques.
- Experience with RTL quality and sign-off tools (e.g., Lint, CDC).
Preferred qualifications:
- Experience integrating third-party vendor IPs (such as controllers and PHYs), owning RTL wrappers, timing constraints, UPF, DFT handoffs, and vendor deliverables.
- Experience with PCIe architecture and subsystem integration, or related interconnects and protocols such as Compute Express Link (CXL), Universal Chiplet Interconnect Express (UCIe), or Advanced Extensible Interface (AXI).
- Experience developing scripts, RTL assembly automation, and Electronic Design Automation (EDA) flows (e.g., Python, Tcl).
- Demonstrated eagerness to adopt and pioneer AI-driven tools and workflows across hardware design, integration, and debug.