At Google, you will have the opportunity to find the perfect blend of software design practices and hardware development complexity. As a Test Generator Technical Leader, you will lead the technical development and methodology of advanced pseudo-random test generators and verification tools for Google's custom silicon (ASIC/SoC). You will work at the intersection of hardware and software, driving the strategy for stimuli generation, constraint-solving, and test automation to ensure the functional correctness of next-generation chips. Your strength is primarily in software coding with a good understanding of hardware, or if you are a hardware engineer with software proficiency, this balanced role will let you shine in both disciplines at the same time.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
- Lead the technical design, architecture, and implementation of high-performance test generators and verification frameworks (e.g., using C++, Python, SystemVerilog, or Universal Verification Methodology (UVM).
- Propose, design and implement software automation that directly addresses bottlenecks in today's ASIC and SoC Electronic Design Automation (EDA) flow, specifically targeting pseudo-random stimuli generation and constraint-solving methodology.
- Collaborate directly with the hardware team on projects to prototype and then deploy scalable test generator tools to make a positive impact on Google's chip hardware development process.
- Participate in, or lead design reviews with peers and stakeholders to decide amongst available technologies for advanced verification.
- Triage product or system issues and debug/track/resolve by analyzing the sources of issues and the impact on hardware, simulation performance, or service operations and quality.
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 8 years of experience with software development in one or more programming languages with experience in data structures and algorithms.
- Experience in hardware verification, building developer tools, or developing test generators/exercisers for ASICs and SoCs.
- Experience testing, maintaining, or launching software/hardware products.
- Experience with software design and architecture, including leading technical projects.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with an emphasis on computer architecture.
- Experience with high-performance, systems, and debugging.
- Experience with Hardware Verification languages and methodologies (e.g., SystemVerilog, UVM).
- Experience in chip design and related EDA tools and flows (e.g., VCS, Xcelium, debugging complex hardware-software interactions).
- Deep understanding of object-oriented programming, constraint solvers, and software design architecture.
- Software skills and design practices, with the ability to bridge the gap between software engineering and hardware verification disciplines.