In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
In this role, you will collaborate with functional design, Design for Testing (DFT), architecture, and packaging engineers. You will solve technical problems with innovative micro-architecture and practical logic circuits solutions, while evaluating design options with optimized performance, and power.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Responsibilities
- Define and drive the implementation of physical design methodologies. Define the physical design related rule sets for the functional design engineers.
- Work closely with power architects and produce detailed trade-off analysis of impact of Power Delivery Network (PDN) on different use-case power.
- Work on system and block level simulations (e.g., IR drop, electromigration).
- Take ownership of one or more physical design partitions or top level.
- Drive to the closure of timing and power consumption of the design. Contribute to design methodology, libraries, and code review.
Minimum qualifications:
- Bachelor’s degree in Electrical Engineering or equivalent practical experience.
- 4 years of experience in power delivery network design and verification in nodes technologies.
- Experience with Electromigration (EM)/IR tools (e.g., RedHawk-SC, Totem, Voltus, Spice).
- Experience scripting in TCL, Python, or C++.
Preferred qualifications:
- Master’s degree in Electrical Engineering.
- Experience with power components, modeling/trees/network design.
- Experience in battery droop mitigation, overcurrent protection, thermal shutdown.
- Experience in power consumption estimation/calculation of System-on-a-Chip (SoC).
- Familiarity with low power design techniques (e.g., power/voltage domain design, clock gating, power gating, dynamic voltage frequency scaling).