Responsibilities
- Develop methodology of SoC roll up of power reduction, projection, configuration, test plan and tools.
- Work intact with Architecture, Frontend and Backend teams driving power reduction features (both logic and circuit).
- Work with power delivery and packaging teams on simulations and scenario definitions.
- Work with Architecture and design verification (DV) to define power scenarios and tests, debug, and integrate into the flow. Track whether power goals are met throughout execution.
- Lead the power of a project. Own project priorities, and allocation of technical resources within the project, informing and escalating appropriately when external factors impact execution.
Minimum qualifications:
- Bachelor's degree in Computer Science, Electrical Engineering, or a related technical field, or equivalent practical experience.
- 8 years of experience in power estimation and optimization flows and tools.
- Experience with vector based physical design power tools (e.g., PTPX prime power).
Preferred qualifications:
- Experience with power optimization techniques (multiple threshold voltage/power/voltage domain design, clock gating, power gating, dynamic voltage and frequency scaling (DVFS)/adaptive voltage scaling (AVS), etc.) and power management.
- Experience with scripting languages (i.e., Python, Perl, TCL or Bash).
- Experience in post silicon measurements, telemetry, correlation to pre-silicon.
- Knowledge of the impact of software and architectural design decisions on power and thermal behavior of the system (thermal mitigation and scheduling, cross-layer policy design).
- Knowledge of system software components (i.e., Linux, drivers, runtime performance analysis, etc.).
- Knowledge of register-transfer level (RTL) micro-architecture and design for power.